### VERILOG LANGUAGE ###

#   ELEMENT_NAME [optional-css-class] REGULAR_EXPRESSION

    NAME                Verilog
    VERSION             1.0

    COMMENT             (?default)
    PREPROCESSOR        (?default)
    STRING              (?default)

    STATEMENT           \b(?alt:statement.txt)\b
    RESERVED            \b(?alt:reserved.txt)\b
    TYPE                \b(?alt:type.txt)\b
    MODIFIER            \b(?alt:modifier.txt)\b

    ENTITY              (?default)
    VARIABLE            (?default)|(?default:identifier)(?=::)|\b(?<=\-\>)\s*[A-Za-z_]\w*|&(?default:identifier)\s*(?!\()
    IDENTIFIER          (?default)
    CONSTANT            (?default)
    OPERATOR            (?default)
    SYMBOL              (?default)